1. Field of the Invention
The present invention is related to processing of silicon-based integrated circuits, and, more particularly, to etching of polysilicon used in devices in such circuits.
2. Description of the Related Art
In many silicon-based devices, particularly CMOS (complementary metal oxide semiconductor), both n-type and p-type polysilicon are used. For example, n-type polysilicon is used as the gate electrode and/or electrode making a "buried contact" for n-channel devices; p-type polysilicon is used as the gate electrode and/or "buried contact" for p-channel devices. Often, the polysilicon is formed as layers on the same level, and it is desired to etch both n-type and p-type layers, simultaneously.
Usually, n-type polysilicon etches at a much faster rate than p-type polysilicon in conventional plasma etching apparatus, employing fluorinated or chlorinated plasma, generated from gases such as SF.sub.6, Cl.sub.2, CCl.sub.4, Freons, etc. A process has been developed for use with separate wafers, each wafer having solely one or the other material may be etched at about the same rate. In this process, a mixture of Cl.sub.2 and BCl.sub.3 is employed to anisotropically etch polycide (n.sup.+ or p.sup.+ polysilicon with MoSi.sub.2 cap). The process is described by T. C. Mele et al, "Anisotropic Reactive Ion Etching of MoSi.sub.2 and In-Situ Doped N.sup.+ and P.sup.+ Polysilicon Using Cl.sub.2 and BCl.sub.3 ", Semiconductor Research Corporation, Sept. 22, 1987.
At the present time, it is not possible to etch both n- and p-type polysilicon layers simultaneously on the same wafer. The ability to do so would improve the processing efficiency of silicon devices and provide a flexibility in developing architecture, particularly CMOS devices.